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Agilent HCPL-7723 & HCPL-0723 50 MBd 2 ns PWD High Speed CMOS Optocoupler Data Sheet
Description Available in either 8-pin DIP or SO-8 package style respectively, the HCPL-7723 or HCPL-0723 optocoupler utilize the latest CMOS IC technology to achieve outstanding speed performance of minimum 50 MBd data rate and 2 ns maximum pulse width distortion.
Basic building blocks of HCPL7723/0723 are a CMOS LED driver IC, a high speed LED and a CMOS detector IC. A CMOS logic input signal controls the LED driver IC, which supplies current to the LED. The detector IC incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver.
Functional Diagram
**VDD1
1
8
VDD2**
VI
2 IO
7
NC*
Features * +5 V CMOS compatibility * High speed: 50 MBd min. * 2 ns max. pulse width distortion * 22 ns max. prop. delay * 16 ns max. prop. delay skew * 10 kV/s min. common mode rejection * -40 to 85C temperature range * Safety and regulatory approvals (Pending) UL recognized - 2500 V rms for 1 min. per UL1577 for HCPL-7723 - 3750 V rms for 1 min. per UL1577 for HCPL-0723 CSA component acceptance notice #5 VDE 0884 - Viorm = 630 Vpeak for HCPL-7723 option 060 - Viorm = 560 Vpeak for HCPL-0723 option 060 Applications * Digital fieldbus isolation: CC-Link, DeviceNet, Profibus, SDS * Isolated A/D or D/A conversion * Multiplexed data transmission * High Speed Digital Input/Output * Computer peripheral interface * Microprocessor system interface
*
3 LED1
6
VO
GND1
4 SHIELD
5
GND2
* PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE. PIN 7 IS NOT CONNECTED INTERNALLY. ** A 0.1 F BYPASS CAPACITOR MUST BE CONNECTED BETWEEN PINS 1 AND 4, AND 5 AND 8. TRUTH TABLE (POSITIVE LOGIC) VI, INPUT H L LED1 OFF ON VO, OUTPUT H L
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by ESD.
Package Outline Drawings HCPL-7723 8-Pin DIP Package
9.65 0.25 (0.380 0.010) TYPE NUMBER 8 7 6 5 OPTION 060 CODE*
7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) DATE CODE
A XXXXV YYWW 1 1.19 (0.047) MAX. 2 3 4
1.78 (0.070) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
5 TYP. 4.70 (0.185) MAX.
0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). *OPTION 300 AND 500 NOT MARKED.
1.080 0.320 (0.043 0.013)
0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010)
2
HCPL-7723 Package with Gull Wing Surface Mount Option 300
PAD LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
8 7 6 5
1.016 (0.040) 1.194 (0.047)
4.826 TYP. (0.190) 6.350 0.25 (0.250 0.010) 9.398 (0.370) 9.906 (0.390)
1
2
3
4
1.194 (0.047) 1.778 (0.070) 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)
0.381 (0.015) 0.635 (0.025)
1.19 (0.047) MAX.
4.19 MAX. (0.165)
+ 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
1.080 0.320 (0.043 0.013) 2.54 (0.100) BSC 0.635 0.130 (0.025 0.005)
0.635 0.25 (0.025 0.010)
12 NOM.
DIMENSIONS IN MILLIMETERS AND (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
HCPL-0723 Small Outline SO-8 Package
TYPE NUMBER
8
7
6 XXXV YWW
5
5.842 0.203 (0.236 0.008) OPTION 060 CODE*
3.937 0.127 (0.155 0.005)
1 0.381 0.076 (0.016 0.003)
2
3
4 1.270 BSG (0.050)
DATE CODE
5.080 0.005 (0.200 0.005) 3.175 0.127 (0.125 0.005)
7
45 X 0.432 (0.017)
1.524 (0.060) 0.152 0.051 (0.006 0.002)
0.228 0.025 (0.009 0.001)
DIMENSIONS IN MILLIMETERS AND (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). *OPTION 500 NOT MARKED.
0.305 MIN. (0.012)
3
Device Selection Guide 8-Pin DIP (300 mil) HCPL-7723 Small Outline SO-8 HCPL-0723
Ordering Information Specify Part Number followed by Option Number (if desired) Example: HCPL-7723-XXX 060 = VDE0884 Option. 300 = Gull Wing Surface Mount Option (HCPL-7723 only). 500 = Tape and Reel Packaging Option. No Option and Option 300 contain 50 units (HCPL-7723), 100 units (HCPL-0723) per tube. Option 500 contain 1000 units (HCPL-7723), 1500 units (HCPL-0723) per reel. Option data sheets available. Contact sales representative or authorized distributor.
4
Solder Reflow Temperature Profile
300
PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C PEAK TEMP. 230C 2.5C 0.5C/SEC. 160C 150C 140C 3C + 1C/-0.5C 30 SEC. 30 SEC. SOLDERING TIME 200C
TEMPERATURE (C)
200
100
PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE
ROOM TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
Regulatory Information The HCPL-7723/0723 will be approved by the following organizations: UL Recognized under UL1577, component recognition program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA88324.
VDE (HCPL-7723 option 060) Approved according to VDE 0884/06.92, File 6591-23-48801005. TUV Rheinland (HCPL-0723 Option 060) Approved according to VDE 0884/06.92, Certificate R9650938.
Insulation and Safety Related Specifications Value Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Symbol L(I01) L(I02) 7723 7.1 7.4 0.08 0723 4.9 4.8 0.08 Units mm mm mm Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Insulation thickness between emitter and detector; also known as distance through insulation. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
175 IIIa
175 IIIa
Volts
5
All Agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit
board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered.
There are recommended techniques such as grooves and ribs, which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
VDE 0884 Insulation Related Characteristics (Option 060) Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 150 V rms for rated mains voltage 300 V rms for rated mains voltage 450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC VIORM VPR Symbol HCPL-7723 Option 060 I-IV I-IV I-III 55/85/21 2 630 1181 HCPL-0723 Option 060 I-IV I-III 55/85/21 2 560 1050 V peak V peak Units
VPR
945
840
V peak
Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (maximum values allowed in the event of a failure, also see Thermal Derating curve, Figure 11) Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V
VIOTM
6000
4000
V peak
175 TS 230 IS,INPUT PS,OUTPUT 600 RIO 109
150 150 600 109
C mA mW
*Refer to the front of the optocoupler section of the Isolation and Control Component Designer's Catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Note: The surface mount classification is Class A in accordance with CECC 00802.
6
Absolute Maximum Ratings Parameter Storage Temperature Ambient Operating Temperature[1] Supply Voltages Input Voltage Output Voltage Average Output Current Lead Solder Temperature Solder Reflow Temperature Profile Symbol TS TA VDD1 , VDD2 VI VO IO Min. -55 -40 0 -0.5 -0.5 Max. 125 85 6.0 VDD1 +0.5 VDD2 +0.5 10 Units C C Volts Volts Volts mA
260C for 10 sec., 1.6 mm below seating plane See Solder Reflow Temperature Profile Section
Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltages Logic High Input Voltage Logic Low Input Voltage Input Signal Rise and Fall Times Symbol TA VDD1 , VDD2 VIH VIL tr, tf Min. -40 4.5 2.0 0.0 Max. 85 5.5 VDD1 0.8 1.0 Units C V V V ms
Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25C, VDD1 = VDD2 = +5 V. Parameter Logic Low Input Supply Current[2] Logic High Input Supply Current [2] Output Supply Current Input Current Logic High Output Voltage Logic Low Output Voltage Symbol IDD1L IDD1H IDD2L IDD2H II VOH VOL -10 4.4 4.0 5.0 4.8 0 0.5 0.1 1.0 Min. Typ. 7 1.8 12.5 12 Max. 10 3 17.5 16.5 10 Units mA mA mA mA A V V V V IO = -20 A, VI = VIH IO = -4 mA, V I = VIH IO = 20 A, VI = VIL IO = 4 mA, V I = VIL Test Conditions VI = 0 V VI = VDD1
7
Switching Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at T A = +25C, VDD1 = VDD2 = +5 V. Parameter Propagation Delay Time to Logic Low Output[3] Propagation Delay Time to Logic High Output[3] Pulse Width Maximum Data Rate Pulse Width Distortion[4] |t PHL - tPLH| Propagation Delay Skew[5] Output Rise Time (10% - 90%) Output Fall Time (90% - 10%) Common Mode Transient Immunity at Logic High Output[6] Common Mode Transient Immunity at Logic Low Output[6] |PWD| tPSK tR tF |CMH| |CML| 10 10 8 6 15 15 Symbol t PHL tPLH PW 20 50 1 2 16 Min. Typ. 16 16 Max. 22 22 Units ns ns ns MBd ns ns ns ns kV/s kV/s Test Conditions CL = 15 pF CMOS Signal Levels CL = 15 pF CMOS Signal Levels CL = 15 pF CMOS Signal Levels CL = 15 pF CMOS Signal Levels CL = 15 pF CMOS Signal Levels CL = 15 pF CMOS Signal Levels CL = 15 pF CMOS Signal Levels CL = 15 pF CMOS Signal Levels VCM = 1000 V , TA = 25C, VI = VDD1, V O > 0.8 VDD2 VCM = 1000 V , TA = 25C, VI = 0 V , VO < 0.8 V
8
Package Characteristics All Typical Specifications are at T A = 25C. Parameter Input-Output Momentary Withstand Voltage[7,8,9] Input-Output Resistance [7] Input-Output Capacitance Input Capacitance [10] Input IC Junction-to-Case Thermal Resistance Output IC Junction-to-Case Thermal Resistance Package Power Dissipation -7723 -0723 -7723 -0723 -7723 -0723 Symbol Min. V ISO R I-O C
I-O
Typ.
Max.
Units V rms
Test Conditions RH 50%, t = 1 min, T A = 25C VI-O = 500 V dc f = 1 MHz Thermocouple located at center underside of package
2500 3750 10 12 0.6 3.0 145 160 145 135 150
pF pF C/W C/W mW
CI jci jco PPD
Notes: 1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee functionality. 2. The LED is ON when VI is low and OFF when VI is high. 3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 4. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width. 5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 7. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 8. In accordance with UL1577, each HCPL-0723 is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit, II-O 5 A). Each HCPL-7723 is proof tested by applying an insulation test voltage 3000 Vrms for 1 second (leakage detection current limit. II-O 5 A.) 9. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." 10. CI is the capacitance measured at pin 2 (VI).
9
Application Information Bypassing and PC Board Layout The HCPL-7723/0723 optocouplers are extremely easy to use. No external interface circuitry is required because the HCPL-7723/0723 use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 1, the only external components required for proper operation are two bypass capacitors. Capacitor values
should be between 0.01 F and 0.1 F. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 2 illustrates the recommended printed circuit board layout for the HCPL-7723/ 0723. Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit which describes how quickly a logic signal propagates through
a system as illustrated in Figure 3. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low.
VDD1 C1 VI
1
HCPL-7723 OR HCPL-0723
8 C2 7 NC 6 5 GND2
VDD2
2 NC 3 GND1 4
VO
C1, C2 = 0.01 F TO 0.1 F
Figure 1. Functional diagram.
VDD1
VDD2
HCPL-7723 OR HCPL-0723
VI C1
C2 VO GND2 C1, C2 = 0.01 F TO 0.1 F
GND1
Figure 2. Recommended printed circuit board layout.
INPUT VI tPLH OUTPUT VO 90% 10% tPHL 90%
5 V CMOS 50% 0V
10%
VOH 2.5 V CMOS VOL
Figure 3. Timing diagram to illustrate propagation delay, tplh and tphl.
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Pulse-width distortion (PWD) is the difference between tPHL and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable. Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of
optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As
illustrated in Figure 4, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or t PHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 5 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. In this case the data is assumed to be clocked off of the rising edge of the clock. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 5 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK . A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The HCPL-7723/0723 optocouplers offer the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges.
VI
50%
VO
2.5 V, CMOS tPSK
VI
50%
VO
2.5 V, CMOS
Figure 4. Timing diagram to illustrate propagation delay skew, tpsk.
DATA INPUTS CLOCK
DATA OUTPUTS CLOCK tPSK tPSK
Figure 5. Parallel data transmission example.
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www.agilent.com/semiconductors
For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright (c) 2002 Agilent Technologies, Inc. December 2, 2002 5988-7986EN

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